1. Technical Field of the Invention
This invention relates to the testing of computer system designs by software simulation facilitated by a physical simulation machine, or accelerator, and more particularly to applying a binary convergence algorithm to generate sampling values to optimize accelerator cycles.
2. Background Art
The complexity and sophistication of present-day integrated circuit (IC) chips have advanced significantly over those of early chip designs. Where formerly a chip might embody relatively simple electronic logic blocks effected by interconnections between logic gates, currently chips can include combinations of complex, modularized IC designs often called “cores” which together constitute an entire “system-on-a-chip”, or SOC.
In general, IC chip development includes a design phase and a verification phase for determining whether a design works as expected. The verification phase has moved increasingly toward a software simulation approach to avoid the costs of first implementing designs in hardware to verify them.
A key factor for developers and marketers of IC chips in being competitive in business is time-to-market of new products; the shorter the time-to-market, the better the prospects for sales. Time-to-market in turn depends to a significant extent on the duration of the verification phase for new products to be released.
As chip designs have become more complex, shortcomings in existing chip verification methodologies which extend time-to-market have become evident.
Typically, in verifying a design, a simulator is used. Here, “simulator” refers to specialized software whose functions include accepting software written in a hardware description language (HDL) such as Verilog or VHDL, which models a circuit design (for example, a core as described above), and using the model to simulate the response of the design to stimuli which are applied by a test case to determine whether the design functions as expected. The results are observed and used to de-bug the design.
In order to achieve acceptably bug-free designs, verification software must be developed for applying a number of test cases sufficient to fully exercise the design in simulation. In the case of System-on-chip (SOC) designs, the functioning of both the individual cores as they are developed, and of the cores interconnected as a system must be verified.
Hardware assisted simulation (or acceleration) has the potential of providing a very high performance environment for digital logic simulation.
As opposed to a pure software simulator, an accelerator consists of a specialized physical simulation machine (the accelerator), connected by cable to a port on a physical host computer. The digital logic being simulated is synthesized and loaded into the machine, and a software device driver in the host computer interacts with the machine.
Test cases for the system, in the context of this invention, consist of sequences of bus transactions that originate in software application code, such as the IBM Test Operating System or other firmware applications, and are driven into the accelerator.
Within the logic of the loaded design, are a set of Bus Functional Models (BFMs) that contain interface registers for driving the transactions. Each BFM supports a specific type of transaction such as Device Control Register (DCR) or Processor Local Bus (PLB) reads, or PLB writes, for example.
Driving transactions means reading and writing BFM registers values in the logic hierarchy of the loaded design, thru the device driver, and programming the accelerator to run a certain number of samples to execute the desired transaction.
The accelerator's performance is maximized when it has lots of samples to directly execute, with minimum interaction with the host computer. The test application software runs at a much higher speed than the accelerator. Overall system thruput is therefore determined by the performance of the accelerator, and the rate that the software can deliver transactions, and is maximized by the correct balance of the two.
A test case consists of a sequence of transactions, different types of reads and writes, issued to multiple BFMs in the design. The actual number of samples it takes to complete a transaction varies according to BFM type and design element interactions. An automated method of optimized balance between the number of samples given to the accelerator and the workload (sequence of transactions) is needed. The method needs to be ambivalent to the actual logic design being simulated, and the dynamic interactions within the design. Current art uses worst case sampling, or empirically determined sampling values (based on design specifications). This approach can either starve the test application (by over-sampling the accelerator), or cause too much host computer interaction (by under-sampling the accelerator). In either case, overall thruput is compromised.